The present invention relates to a digital radio receiver using a sequential decoder for decoding convolutional codes.
In order to detect errors in transmitted data bits and correct the data bits in error, the current practice involves segmenting data to be transmitted into several information symbols and converting them into convolutionally coded symbols using a forward error correction encoder and decoding transmitted symbols by an error correction decoder according to an algorithm which is known as the Fano algorithm.
According to the Fano algorithm developed by R. M. Fano and described in IEEE Transactions on Information Theory, IT-9 (1963), pages 64-74, the signal received by a decoder for hard-decision decoding does not necessarily match what is actually transmitted due to lost or corruption of data bits or due to ambiguities present in the amplitude levels of demodulated QAM or PSK signals resulting from phase errors introduced to the recovered carrier. If the decoder performs its decoding step on a per codeword basis, the decoder can be said to have the same circuit function as the error correction encoder, or a "replica of the encoder". On receiving a codeword, the decoder compares it with each of codewords which the replica of the encoder would produce if it were to receive all possible information symbols and assumes an information symbol that is nearest to the received codeword. The yardstick which is currently employed for measuring the distance to the nearest codeword is the Fano likelihood algorithm. According to the Fano algorithm, an information symbol sequence which gives the largest cumulative value is assumed to be the most likely message sequence.
If a large number of burst errors should occur, there is a possibility that the decoder makes a false decision. After making an incorrect decision, the discrepancies between the internal states of the encoder replica and those in the encoder grow much more rapidly than would be the case if the decoder were following the correct path, and all subsequent attempts would fail to find symbols having a large Fano likelihood value, thus making it possible to detect that a false decision has been made in the past. On detecting a false decision, the decoder retraces its path to return the internal states of the encoder replica to a point where the false decision was possibly made and takes an alternate path that gives the next largest cumulative value of the Fano likelihood and performs a decoding step on the selected path. If the decoder should fail in the search, it retraces further back to a past state to repeat the process. In this way, the decoder attempts to search for a correct path on the basis of trial and error. Since the past histories are retraced in the sequential decoder, the input and output symbols are stored in respective input and output buffers. The error correction encoder and decoder mentioned above can be implemented by a circuit shown and described in U.S. Pat. No. 3,665,396 issued to George David Forney, Jr.
In order to achieve the comparison between the output codeword of the encoder replica and the input bit sequence to that replica, the decoder must be able to detect the boundary point of each bit sequence. Thus, the comparison should be performed in synchronism with the boundary point each received bit sequence. Since the received symbol does not usually contain codeword timing information, the prior art sequential decoder performs the code resynchronization process on a trial and error basis.
Since out-of-word timing conditions can result in a situation which is equivalent to the occurrence of a serious transmission error, the decoding process encounters a substantial amount of delay, tending to overflow the input buffer. Such overflow conditions can thus be taken as an indication of the occurrence of an out-of-word timing condition. On detecting an overflow, the decoder shifts the codeword boundary timing by one clock pulse before proceeding to decode on a trial basis a fresh bit sequence entered next into the input buffer. If this trial attempt still does not work to alleviate the overflow, the same process is repeated. Assume that the codeword is made up of n coded bits, there are n possible states which can be retraced to reestablish synchronism. A single unsuccessful trial attempt for resynchronization will cause the input buffer to store the maximum number of symbols that can be stored therein. The maximum amount of time taken to resynchronize the decoder is therefore (n-1) times the interval taken to store the maximum number of symbols into the input buffer. In addition, whole symbols stored in the input buffer must be discarded whenever a resynchronization is attempted. The resynchronization attempt of the prior art sequential decoder can therefore take as long as (n-1) times the whole storage time of the input buffer, and no input data can be received during that interval.
Another important factor that influences the sequential decoding process is the well-known phase ambiguity of orthogonally modulated signals such as 4PSK (phase shift keyed) or 16 QAM (quadrature amplitude modulation) signals associated with the recovered carrier phase at the receiver. Thus, phase differences of an integral multiple of 90 degrees can occur in the case of 4PSK between the transmitted carrier and the recovered carrier. Since the orthogonal modulation employs a technique of alternately separating a bit sequence into two bit groups corresponding to in-phase (P) and quadrature-phase (Q) channels, respectively, the phase differences can result in bit reversals and transposition of channels. For example, a phase error of 90 degrees of a transmitted 4PSK symbol "01" may be converted to "00" and a phase error of 180 degrees of the "01" symbol may be converted to "10".